Phase locked loops (PLLs) can provide precise generation and alignment of timing for a wide variety of applications, such as for clock generation or clock data recovery. Digital phase-lock(ed) loops (DPLLs) are a viable alternative to traditional PLLs, in which a digital loop filter can be utilized to replace analog components. For example, DPLLS provide a low-power-small-area solution relative to analog PLLs. In a DPLL the phase offset between a local oscillator (LO) and a reference clock can be measured by an analog-to-digital convertor that can be considered a time-to-digital converter (TDC). The measured phase is then compared to the required/target phase and the result can be used to correct the LO frequency. In DPLL devices, the reference clock can be used to control a faster clock in order to create a clock signal, which is noisy. The fast clock can be an LO such as a voltage controlled oscillator (VCO), and the reference clock can be a crystal (e.g., a crystal oscillator) to monitor and control the LO. However, increasing the reference signal along a reference path generated by the reference clock can increase the in-band noise such as deterministic jitter. Because the oscillator is an important component involved in tuning the DPLL, which can involve coarse tuning and fine tuning operations, eliminating or mitigating the deterministic jitter can improve the operation and efficiency of the DPLL.